FIELD OF THE INVENTION
Programmable non-volatile memory cells have a gate electrode which is in an electrically floating state, the so-called floating gate. The floating gate is isolated by insulating oxide layers both from the channel region of the memory cell, which in other respects is constructed like a MOSFET, and from the control gate electrode of the memory cell, and is arranged between them.
The cell is programmed by a charge applied to the floating gate. The inception voltage, i.e. the voltage at which the MOSFET forming the memory cell starts to conduct, is varied by this charge. When the cell is read, a voltage is applied to the control gate. That voltage has a value which is between the inception voltages of a non-programmed cell and a programmed cell. A logic "0" or a logic "1" is read out depending on whether a current flows as a result.
Until now, two methods have been known relating to how it is possible to apply the charges to the floating gate. In the first method, a high positive voltage of about 12 V is applied to the control gate, while typically about 7 V or 0 V, i.e. the normal operating voltages for MOS circuits, is added to the drain and the source of the MOSFET which forms the memory cell. In consequence, a powerful current flows through the channel of the MOSFET, from which so-called "hot" electrons pass to the floating gate.
In the second method, a high negative voltage of about -12 V is applied to the control gate and a voltage of about 5 V is applied to the drain. In consequence, holes tunnel through the gate oxide to the floating gate and charge it positive. As a result, the inception voltage of the MOSFET which forms the memory cell falls.
The latter method admittedly has the advantage that no leakage current flows through the channel during charging of the floating gate. However, it raises the problem of having to switch a high negative voltage selectively to the word line to be selected. A conventional n-channel MOSFET cannot be used here, since its n-doped drain region or source region would form a virtual short circuit to the p-doped substrate, which is connected to ground, on application of a negative voltage.
It is therefore conventional to arrange n-channel MOSFETs for this purpose in a p-doped well laid through a deep n-doped well. Additional technology outlay is involved here, however, special equipment such as high-energy implanters and the risk of possible charges on the insulated well and gate-oxide stress linked thereto during the processing.
European patent publication EP 0 456 623 A2 discloses another solution. There, the high negative voltage is connected to the word line of a non-volatile memory via p-channel MOSFETs. While the p-MOSFETs can be produced using conventional technology, they require a negative gate voltage for switching. This is produced by voltage inverter circuits from a positive high voltage. However, the voltage inverter circuits are required for each word line, which necessitates considerable circuitry complexity.
A method is described in U.S. Pat. No. 5,311,480 to Schreck wherein a positive voltage is added to all selected word lines through an insulation element. At the same time, only the selected word line is pulled to a negative potential with a charge pump associated therewith. This, however, results in relatively great current consumption.